//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
//Date        : Mon Jun 17 15:39:53 2024
//Host        : lsin-ThinkStation-K-C2490 running 64-bit Ubuntu 23.10
//Command     : generate_target design_1_wrapper.bd
//Design      : design_1_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module design_1_wrapper
   (dip_switch_4bits_tri_i,
    led_4bits_tri_o);
  input [3:0]dip_switch_4bits_tri_i;
  output [3:0]led_4bits_tri_o;

  wire [3:0]dip_switch_4bits_tri_i;
  wire [3:0]led_4bits_tri_o;

  //led 的0,1位接dip_switch的0,1位
  assign led_4bits_tri_o[1:0] = dip_switch_4bits_tri_i[1:0];

  wire [3:0]m_dip_switch_4bits_tri_i;
  wire [3:0]m_led_4bits_tri_o;

  //取led和sw的2,3位，赋值给带m的中间变量，由design_1去处理，将在后续的c语言代码中实现控制逻辑
  assign m_dip_switch_4bits_tri_i[3:2] = dip_switch_4bits_tri_i[3:2];
  assign m_led_4bits_tri_o[3:2] = led_4bits_tri_o[3:2];
  design_1 design_1_i
       (.dip_switch_4bits_tri_i(m_dip_switch_4bits_tri_i),
        .led_4bits_tri_o(m_led_4bits_tri_o));
endmodule
